1.

国際会議録
国際会議録
1. Optimizing manufacturability for the 65-nm process node
Pramanik, D. ; Cote, M.L.
出版情報: Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA.  pp.326-333,  2003.  Bellingham, Wash..  SPIE-The International Society for Optical Engineering
シリーズ名: Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号: 5042
2.

国際会議録
国際会議録
2. Assessing technology options for 65-nm logic circuits
Pramanik, D. ; Cote, M.L. ; Beaudette, K. ; Axelrad, V.
出版情報: Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA.  pp.30-41,  2003.  Bellingham, Wash..  SPIE-The International Society for Optical Engineering
シリーズ名: Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号: 5042
3.

国際会議録
国際会議録
3. Lithography-driven layout of logic cells for 65-nm node
Pramanik, D. ; Cote, M.L.
出版情報: Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA.  pp.126-134,  2003.  Bellingham, Wash..  SPIE-The International Society for Optical Engineering
シリーズ名: Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号: 5042