Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology

Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology

著者名:

Adrichem, P.J.M. ( Numerical Technologies Inc. (Netherlands) )
Driessen, F.A.J.M. ( Numerical Technologies Inc. (Netherlands) )
Hasselt, K. ( Philips Semiconductors (Netherlands) )

掲載資料名:

Metrology, Inspection, and Process Control for Microlithography XVII

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5038

発行年:

2003

巻:

2

開始ページ:

1019

終了ページ:

1025

総ページ数:

7

出版情報:

Bellingham, WA: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819448439 [0819448435]

言語:

英語

請求記号:

P63600/5038

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00013025
シリーズID:	PA00000029
会議名:	SPIE Advanced Lithography : Metrology, Inspection, and Process Control for Microlithography
回次:	2003 : 17th
会議開催地:	Santa Clara, California, USA
会議開催年:	2003.02.24-2003.02.27
論文注記:	Poster Session ; 5038-127

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