FPGA chip performance improvement with gate shrink through alternating PSM 9Onm process [5992-182]

FPGA chip performance improvement with gate shrink through alternating PSM 9Onm process [5992-182]

著者名:

Yu, C. -C.

Shieh, M. -F.

Liu, E.

Lin, B. ( UMC (Taiwan) )

Ho, J.

Wu, X. ( Xilinx Inc. (USA) )

Panaite, P.

Chacko, M.

Zhang, Y.

Lei, W. ( Synopsys Inc. (USA) )

さらに 5 件

掲載資料名:

25th Annual BACUS Symposium on Photomask Technology

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5992

発行年:

2005

パート:

2

開始ページ:

59925A

出版情報:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819460141 [0819460141]

言語:

英語

請求記号:

P63600/5992

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00016029
シリーズID:	PA00000029
会議名:	SPIE Photomask Technology : Annual BACUS Symposium on Photomask Technology
回次:	2005 : 25th
会議開催地:	Monterey, California, USA
会議開催年:	2005.10.04-2005.10.07

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