Planar Bonded Double Gate MOS Transistors Down to LG = 10 nm (Invited paper)

Planar Bonded Double Gate MOS Transistors Down to LG = 10 nm (Invited paper)

著者名:

Vinet, M.

掲載資料名:

ULSI Process Integration : proceedings of the International Symposium

シリーズ名:

Electrochemical Society Proceedings Series

シリーズ巻号:

2005-06

発行年:

2005

開始ページ:

285

終了ページ:

295

総ページ数:

11

出版情報:

Pennington, N.J.: Electrochemical Society

ISSN:

01616374

ISBN:

9781566774642 [1566774640]

言語:

英語

請求記号:

E23400/200506

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00015389
シリーズID:	PA00000028
会議名:	International Symposium on ULSI Process Integration ; Meeting of the Electrochemical Society
回次:	4th ; 207th
会議開催地:	Quebec, Canada
会議開催年:	2005.05.16-2005.05.20

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