61 Impact of Recessed S/D SiGe Integration Parameters on Device Performance

61 Impact of Recessed S/D SiGe Integration Parameters on Device Performance

著者名:

Washington, L.

掲載資料名:

Advanced gate stack, source/drain and channel engineering for Si-based CMOS, new materials, processes, and equipment : proceedings of the international symposium

シリーズ名:

Electrochemical Society Proceedings Series

シリーズ巻号:

2005-05

発行年:

2005

開始ページ:

515

終了ページ:

522

総ページ数:

8

出版情報:

Pennington, NJ: Electrochemical Society

ISSN:

01616374

ISBN:

9781566774635 [1566774632]

言語:

英語

請求記号:

E23400/200505

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00015388
シリーズID:	PA00000028
会議名:	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS ; Meeting of the Electrochemical Society
回次:	2005 ; 207th
会議開催地:	Quebec City, QC, Canada
会議開催年:	2005.05.16-2005.05.18

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