A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
- 著者名:
- Estrada, A. ( Univ. of Seville (Spain) )
- Jimenez, C. J. ( Univ. of Seville (Spain) )
- Valencia, M. ( Univ. of Seville (Spain) )
- 掲載資料名:
- VLSI Circuits and Systems II
- シリーズ名:
- Proceedings of SPIE - the International Society for Optical Engineering
- シリーズ巻号:
- 5837
- 発行年:
- 2005
- 開始ページ:
- 902
- 終了ページ:
- 912
- 総ページ数:
- 11
- 出版情報:
- Bellingham, Wash.: SPIE - The International Society of Optical Engineering
- ISSN:
- 0277786X
- ISBN:
- 9780819458322 [0819458325]
- 言語:
- 英語
- 請求記号:
- P63600/5837-2
- 資料種別:
- 国際会議録
類似資料:
1
国際会議録
Partitioning and characterization of high speed adder structures in deep-submicron technologies
SPIE - The International Society of Optical Engineering |
Electrochemical Society |
2
国際会議録
Device/Circuit modeling and simulation applied to design of Deep-Submicron SOI CMOS technology
Electrochemical Society |
ESA Publications Division |
3
国際会議録
Electrical Performance and Reliability Aspects of Strain Engineered Deep Submicron CMOS Technologies
Electrochemical Society |
Electrochemical Society |
4
国際会議録
Study of integration issues in shallow trench isolation for deep submicron CMOS technologies
SPIE-The International Society for Optical Engineering |
10
国際会議録
Characterization and Performance Evaluation of an APS Pixel in a Standard 2 um CMOS Technology
Electrochemical Society |
Electrochemical Society |
Electrochemical Society |
SPIE-The International Society for Optical Engineering |
MRS - Materials Research Society |