Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

著者名:

Li, S. ( Cadence Design Systems, Inc. (USA) )

Chen, T. ( ASML MaskTools, Inc. (USA) )

Shah, S. ( Cadence Design Systems, Inc. (USA) )

Joshi, K. ( Cadence Design Systems, Inc. (USA) )

Thumaty, K. ( Cadence Design Systems, Inc. (USA) )

Arora, N. ( Cadence Design Systems, Inc. (USA) )

さらに 1 件

掲載資料名:

Design and process integration for microelectronic manufacturing III : 3-4 March 2005, San Jose, California, USA

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5756

発行年:

2005

開始ページ:

368

終了ページ:

377

総ページ数:

10

出版情報:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819457363 [0819457361]

言語:

英語

請求記号:

P63600/5756

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00014983
シリーズID:	PA00000029
会議名:	SPIE Advanced Lithography : Data analysis and modeling for process control
回次:	2005 : 3rd
会議開催地:	San Jose, CA, USA
会議開催年:	2005.03.03-2005.03.04

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