Blank Cover Image

New OPC methods to increase process margin for sub-70nm devices

著者名:
  • Hong, J. -S. ( SAMSUNG Electronics Co. , Ltd. (South Korea) )
  • Kim, D. -H. ( SAMSUNG Electronics Co. , Ltd. (South Korea) )
  • Kim, S. -W. ( SAMSUNG Electronics Co. , Ltd. (South Korea) )
  • Yoo, M. -H. ( SAMSUNG Electronics Co. , Ltd. (South Korea) )
  • Kong, J. -T. ( SAMSUNG Electronics Co. , Ltd. (South Korea) )
掲載資料名:
Design and process integration for microelectronic manufacturing III : 3-4 March 2005, San Jose, California, USA
シリーズ名:
Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号:
5756
発行年:
2005
開始ページ:
302
終了ページ:
312
総ページ数:
11
出版情報:
Bellingham, Wash.: SPIE - The International Society of Optical Engineering
ISSN:
0277786X
ISBN:
9780819457363 [0819457361]
言語:
英語
請求記号:
P63600/5756
資料種別:
国際会議録

類似資料:

1 国際会議録 DFM based on layout restriction and process window verification for sub-60nm memory devices

S. -H. Choi, D. -H. Jung, J. -S. Hong, J. -H. Choi, M. -H. Yoo, J. -T. Kong

SPIE - The International Society of Optical Engineering
7 国際会議録 Considerations of model-based OPC verification for sub-70nm memory device [6156-39]

Kim, C.-K., Choi, J.-S, Narn, B.-H, Yim, D.

SPIE - The International Society of Optical Engineering
2 国際会議録 Robust and fast OPC approach for metal interconnects of 0.13um logic devices

Park,J.-S., Kim,D.-H., Park,C.-H., Kim,Y.-H., Yoo,M.-H., Kong,J.-T., Kim,H.-W., Yoo,S.-I.

SPIE-The International Society for Optical Engineering
8 国際会議録 Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

Hong, J.-S., Park, C.-H., Kim, D.-H., Choi, S.-H., Ban, Y.-C., Kim, Y.-H., Yoo, M.-H., Kong, J.-T.

SPIE - The International Society of Optical Engineering
3 国際会議録 Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

Soo-Han Choi, Tae-Hoon Park, Eunsung Kim, Hyoung-Joo Youn, Dae-Youp Lee, Yong-Chan Ban, A-Young Je, Dong-Hyun Kim, …

SPIE - The International Society of Optical Engineering
9 国際会議録 25 nm immersion lithography at 193 nm wavelength

Choi, S.-H., Park, T.-H., Kim, E., Youn, H.-J., Lee, D.-Y., Ban, Y.-C., Je, A.-Y., Kim, D.-H., Hong, J.-S., Kim, Y.-H., …

SPIE - The International Society of Optical Engineering
4 国際会議録 OPC and verification accuracy enhancement using the 2D wafer image for the low kl memory devices [6154-19]

Ban, Y. C., Lee, D. Y., Hong, J. S., Yoo, M. H., Kong, J.-T.

SPIE - The International Society of Optical Engineering
10 国際会議録 MEEF-based correction to achieve OPC convergence of low-kl lithography with strong OAI [6154-25]

Choi, S. H., Je, A Y., Hong, J. S., Yoo, M.-H, Kong, J.-T

SPIE - The International Society of Optical Engineering
5 国際会議録 Efficient OPC model generation and verification for focus variation [6154-128]

Park, Y. H., Ban, Y. C., Hur, D. H., Kim, D. -H., Hong, J. -S., Yoo, M. -H., Kong, J. T.

SPIE - The International Society of Optical Engineering
11 国際会議録 A method for generating assist-features in full-chip scale and its application to contact layers of sub-70nm DRAM devices

D. Park, S. Kim, C. Hwang, S. Lee, H. Cho, J. Moon

SPIE - The International Society of Optical Engineering
6 国際会議録 Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node

Choi, S.-H., Park, J.-S., Park, C.-H., Chung, W.-Y., Kim, I.-S., Kim, D.-H., Kim, Y.-H., Yoo, M.-H., Kong, J.-T.

SPIE-The International Society for Optical Engineering
12 国際会議録 Spin-on organic hardmask materials in 70nm devices

C. Oh, D. Uh, D. Kim, J. Lee, H. Yun, I. Nam, M. Kim, K. Yoon, K. Hyung, N. Tokareva, H. Cheon, J. Kim, T. Chang

SPIE - The International Society of Optical Engineering
1
 
2
 
3
 
4
 
5
 
6
 
7
 
8
 
9
 
10
 
11
 
12