Resolution enhancement technique optimization using model-based full-chip verification methodology for subwavelength lithography

Resolution enhancement technique optimization using model-based full-chip verification methodology for subwavelength lithography

著者名:

Kim, J. ( Synopsys, Inc. (USA) )
Fan, M. ( Synopsys, Inc. (USA) )
Wang, L. ( Synopsys, Inc. (USA) )
Tsuei, T. ( Synopsys, Inc. (USA) )
Tang, Z. ( Synopsys, Inc. (USA) )

掲載資料名:

24th Annual BACUS Symposium on Photomask Technology

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5567

発行年:

2004

開始ページ:

1168

終了ページ:

1177

総ページ数:

10

出版情報:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819455130 [081945513X]

言語:

英語

請求記号:

P63600/5567-2

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00014770
シリーズID:	PA00000029
会議名:	Annual BACUS Symposium on Photomask Technology
回次:	2004 : 24th
会議開催地:	Monterey, CA, USA
会議開催年:	2004.09.14-2004.09.17

類似資料:

1 国際会議録 Contact CD variation check and contact/metal overlay check using a model based full chip verification software tool [5853-41] Wang, L., Kim, J., Zhang, D., Tang, Z., Fan, M. SPIE - The International Society of Optical Engineering	7 国際会議録 Resolution enhancement techniques and mask manufacturability for subwavelength lithography Karklin,K., Lin,B.J. SPIE - The International Society for Optical Engineering
2 国際会議録 Full-chip level MEEF analysis using model based lithography verification [5992-95] Kim, J., Wang, L., Zhang, D., Tang, Z. SPIE - The International Society of Optical Engineering	8 国際会議録 Full-chip application for SRAM gate at 100-nm node and beyond using chromeless phase lithography Park, J.-S., Kim, S.-H., Shin, I.-K., Choi, S.-W., Sohn, J.-M., Lee, J.-H., Shin, H.-S., Laidig, T.L., Van den Broeke, … SPIE - The International Society of Optical Engineering
3 国際会議録 Model-based full-chip verification for 65nm lithography process development [5853-42] Kim, J., Wang, L., Zhang, D., Tang, Z. SPIE - The International Society of Optical Engineering	9 国際会議録 Accurate gate CD control through the full-chip area using the dual model in the model-based OPC Hong, J.-S., Park, C.-H., Kim, D.-H., Choi, S.-H., Ban, Y.-C., Kim, Y.-H., Yoo, M.-H., Kong, J.-T. SPIE - The International Society of Optical Engineering
4 国際会議録 Full-chip poly gate critical dimension control using model based lithography verification [5992-186] Zhang, D. N., Kim, J., Tang, Z. SPIE - The International Society of Optical Engineering	10 国際会議録 65-nm full-chip implementation using double dipole lithography Hsu, S.D., Chen, J.F., Cororan, N., Knose, W.T., Broeke, D.J.V.D., Laidig, T.L., Wampler, K.E., Shi, X., Hsu, C.M., … SPIE-The International Society for Optical Engineering
5 国際会議録 Hotspot detection on post-OPC layout using full-chip simulation-based verification tool: a case study with aerial image simulation Kim, J., Fan, M. SPIE - The International Society of Optical Engineering	11 国際会議録 Fast and accurate 3D mask model for full-chip OPC and verification P. Liu, Y. Cao, L. Chen, G. Chen, M. Feng, J. Jiang, H. Liu, S. Suh, S. Lee SPIE - The International Society of Optical Engineering
6 国際会議録 Increasing post OPC layout verification coverage using a full-chip simulation based verification method Hung, C.-Y., Wang, Y. D., Deng, Z. X., Gao, G. S., Fan, M. H. SPIE - The International Society of Optical Engineering	12 国際会議録 Predictive focus exposure modeling (FEM) for full-chip lithography [6154-66] Chen, L., Cao Y, Liu H, Shao W, Feng M, Ye, J SPIE - The International Society of Optical Engineering

1

2

3

4

5

6

7

8

9

10

11

12