Comparison of partially and fully depleted SOI transistors down to the sub 50-nm-gate length regime | 東京科学大学図書館文献データベース

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Comparison of partially and fully depleted SOI transistors down to the sub 50-nm-gate length regime

著者名:

Dreeskornfeld, L.

Schmitt-Landsiedel, D.

さらに 4 件

掲載資料名:

Silicon-on-insulator technology and devices XI : proceedings of the international symposium

シリーズ名:

Electrochemical Society Proceedings Series

シリーズ巻号:

2003-5

発行年:

2003

開始ページ:

361

終了ページ:

366

総ページ数:

6

出版情報:

Pennington, N.J.: Electrochemical Society

ISSN:

01616374

ISBN:

9781566773751 [156677375X]

言語:

英語

請求記号:

E23400/200305

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00014068
シリーズID:	PA00000028
会議名:	International Symposium on Silicon-on-Insulator Technology and Devices ; Meeting of the Electrochemical Society
回次:	11th ; 203rd
会議開催地:	Paris, France
会議開催年:	2003.04.28-2003.05.02

類似資料:

1 国際会議録 Physically based simulation of fully depleted SOI MOS transistors at nanometer gate lengths A. Burenkov, C. Kampen, J. Lorenz, H. Ryssel Society of Photo-optical Instrumentation Engineers	7 国際会議録 Steady-state characterization of partially depleted SOI CMOS gates Bracale, A., Dupont-Nivet, E., Pelloje, J.-L. Electrochemical Society
2 国際会議録 Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation Yawei Jin, Lei Ma, Chang Zeng, Krishnanshu Dandu, Doug William Barlage Materials Research Society	8 国際会議録 Optical lithography in the sub-50-nm regime Flagello, D.G., Arnold, B., Hansen, S., Dusa, M., Socha, R.J., Mulkens, J., Garreis, R. SPIE - The International Society of Optical Engineering
3 国際会議録 Influence of the Drain Bias and Gate Length of Partially Depleted SOI MOSFETs on the ZTC Biasing Point L.M. Camillo, J.A. Martino, E. Simoen, C. Claeys Electrochemical Society	9 国際会議録 Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 µm Partially-Depleted SOI CMOS Technology L.P. Dantas, S.P. Gimenez Electrochemical Society
4 国際会議録 A. Comparison of C-V and I-V Characteristics of Partially and Fully Depleted Gate-Controlled Diodes Gibki,J., Jakubowski,A., Jurezak,M., Tomaszewski,D. Narosa Publishing House	10 国際会議録 Comparison between Bulk and Floating Body Partially Depleted SOI NMOSFETs for High Frequency Analog Applications Operating from 300 K down to 95 K Pavanello, M. A., Martino, J. A., Simoen, E., Claeys, C. Electrochemical Society
5 国際会議録 Organic Mask Removal Assessment for 32nm Fully Depleted SOI Technology with TiN-metal Gate on HfO2 L. Lachal, J. Chiaroni, E. Lajoinie, O. Louveau, F. Ritton Electrochemical Society	11 国際会議録 Physical and electrical properties of fully-depleted SOI devices Pelloie, J.L., Sun, Y.S. Electrochemical Society
6 国際会議録 Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors M. Galeti, J. A. Martino, E. R. Simoen, C. L. Claeys Electrochemical Society	12 国際会議録 Silicon-On-Insulator (SOI) MOSFET Structure for Sub-50 nm Channel Regime Omura, Y. Electrochemical Society

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