Assessing technology options for 65-nm logic circuits

Assessing technology options for 65-nm logic circuits

著者名:

Pramanik, D. ( Synopsys, Inc. (USA) )
Cote, M.L. ( Synopsys, Inc. (USA) )
Beaudette, K. ( Synopsys, Inc. (USA) )
Axelrad, V. ( Sequoia Design Systems, Inc. (USA) )

掲載資料名:

Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5042

発行年:

2003

開始ページ:

30

終了ページ:

41

総ページ数:

12

出版情報:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819448477 [0819448478]

言語:

英語

請求記号:

P63600/5042

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00013033
シリーズID:	PA00000029
会議名:	Microelectronic Manufacturing : Design and process integration for microelectronic manufacturing
回次:	2003 : 2nd
会議開催地:	Santa Clara, CA, USA
会議開催年:	2003.02.26-2003.02.28

類似資料:

1 国際会議録 Lithography-driven layout of logic cells for 65-nm node Pramanik, D., Cote, M.L. SPIE-The International Society for Optical Engineering	7 国際会議録 Combining OPC and design for printability into 65-nm logic designs Lucas, K.D., Yuan, C.-M., Boone, R., Strozewski, K., Porter, J., Tian, R., Wimmer, K., Cobb, J., Wilkinson, B., Toublan, … SPIE - The International Society of Optical Engineering
2 国際会議録 Optimizing manufacturability for the 65-nm process node Pramanik, D., Cote, M.L. SPIE-The International Society for Optical Engineering	8 国際会議録 ArF lithography options for 100-nm technologies Vandenberghe,G.N., Kim,Y.-C., Delvaux,C., Lucas,K.D., Choi,S.-J., Ercken,M., Ronse,K., Vleeming,B. SPIE-The International Society for Optical Engineering
3 国際会議録 32 nm logic patterning options with immersion lithography K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn Society of Photo-optical Instrumentation Engineers	9 国際会議録 Application of CPL reticle technology for the 65- and 50-nm node Conley, W., Broeke, D.J.V.D., Socha, R.J., Wu, W., Litt, L.C., Lucas, K., Nelson-Thomas, C.M., Roman, B.J., Chen, F., … SPIE-The International Society for Optical Engineering
4 国際会議録 Alt-phase shift mask technology for 65nm logic applications [6154-22] Chakravorty, K. K., Henrichs, S., Qiu, W., Chavez, J. L., Liu, Y.-P., Ghadiali, F., Yung, K., Wilcox, N., Silva, M., Ma, … SPIE - The International Society of Optical Engineering	10 国際会議録 Low k1 lithography patterning option for the 90-nm and 65-nm nodes Hsu, S.D., Van Den Broeke, D.J., Shi, X., Hsu, M., Wampler, K.E., Chen, J.F., Yu, A., Yang, S.C., Hsieh, F. SPIE-The International Society for Optical Engineering
5 国際会議録 High-performance circuit design for the RET-enabled 65-nm technology node Liebmann, L.W., Barish, A.E., Baum, Z., Bonges, H.A., Bukofsky, S.J., Fonseca, C.A., Halle, S.D., Northrop, G.A., … SPIE - The International Society of Optical Engineering	11 国際会議録 Mix and match capability of e-beam direct-write for the 65-nm technology Laplanche, Y., Charpin, M., Pain, L., Todeschini, J., Henry, D., Sassoulas, P.-O., Gough, S., Weidenmueller, U., … SPIE-The International Society for Optical Engineering
6 国際会議録 Integration of CMP into Deep Sub-Micron Multilevel Metallization Circuits Pramanik, D., Weling, M. Electrochemical Society	12 国際会議録 Advances in 193-nm lithography tools Cote,D.R., Ahouse,D., Galburt,D.N., Harrold,H., Kreuzer,J., Nelson,M., Oskotsky,M.L., O'Connor,G., Sewell,H., … SPIE - The International Society for Optical Engineering

1

2

3

4

5

6

7

8

9

10

11

12