15-ps cryogenic operation of 0.19-ｦﾌm-LG n+ - p+ double-gate SOI CMOS | 東京工業大学附属図書館文献データベース

15-ps cryogenic operation of 0.19-ｦﾌm-LG n+ - p+ double-gate SOI CMOS

著者名:

Sugii,T. ( Fujitsu Labs.Ltd. )
Tanaka,T.
Horie,H.
Suzuki,K.

掲載資料名:

Microelectronic Device and Multilevel Interconnection Technology

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

2636

発行年:

1995

開始ページ:

74

終了ページ:

82

出版情報:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819420022 [0819420026]

言語:

英語

請求記号:

P63600/2636

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00019786
シリーズID:	PA00000029
会議名:	SPIE Advanced Lithography : Microelectronic Manufacturing : Microelectronic Device and Multilevel Interconnection Technology
回次:	1995
会議開催地:	Austin, TX, USA
会議開催年:	1995.10.25-1995.10.26

類似資料:

1 国際会議録 A Two-Step, Lightly Nitrided Gate Oxidation process for Sub-0.5ｦﾌm CMOS Technology Roy, P. K., Ma, Y., Flemming, M. T. MRS - Materials Research Society	7 国際会議録 Characterization of Vth fluctuation in O.15-ｦﾌm n-MOSFETs for gigabit DRAM cell transistors Miyashita,T., Suzuki,H., Kojima,M., Nara,Y., Sasaki,N. SPIE-The International Society for Optical Engineering
2 国際会議録 Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10ｦﾌm CMOS Kittl, J. A., Hong, Q. Z., Yang, H., Yu, N., Rodder, M., Apte, P. P., Shiau, W. T., Chao, C. P., Breedijk, T., Pas, M. … MRS - Materials Research Society	8 国際会議録 Optical proximity correction for 0.15-ｦﾌm-rule memory devices Iwasaki,H., Tanabe,H., Inoue,T., Tanaka,Y. SPIE - The International Society for Optical Engineering
3 国際会議録 Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 ｦﾌm CMOS Kittl, J. A., Hong, Q. Z., Yang, H., Yu, N., Rodder, M., Apte, P. P., Shiau, W. T., Chao, C. P., Breedijk, T., Pas, M. … MRS - Materials Research Society	9 国際会議録 Optimization of pre-gate clean technology for a 0.35-ｦﾌm dual-oxide/dual-voltage CMOS process Brugge,H.B., Karnett,M.P., de Muizon,E., Zhou,J., Page,A., Vines,L.B., Haby,B.J. SPIE-The International Society for Optical Engineering
4 国際会議録 FRAM technologies compatible with 0.5-ｦﾌm CMOS logics (Invited Paper) Furumura,Y., Yamazaki,T., Nakamura,M., Inoue,K., Miyazawa,H., Sashida,N., Satomi,R., Katoh,Y., Ozawa,S., Takai,K., … SPIE-The International Society for Optical Engineering	10 国際会議録 High-performance 0.25-ｦﾌm CMOS technology for fast SRAMs Hayden,J.D., McNelly,T.F., Perera,A.H., Pfiester,J.R., Subramanian,C.K., Thompson,M.A. SPIE-The International Society for Optical Engineering
5 国際会議録 Fabrication and characterization of gated Si field emitter arrays with gate aperture below 0.5 ｦﾌm Ku,T.-K., Hsieh,B.B., Chen,M.S., Wang,C.-C., Wang,P.W., Hsieh,I.-J., Cheng,H.-C. SPIE-The International Society for Optical Engineering	11 国際会議録 Merged 2.5-V and 3.3-V 0.25-ｦﾌm CMOS technology Kizilyalli,I.C., Huang,R.Y., Hwang,D., Kane,B.C., Ashton,R., Kuehne,S., Deng,X., Twiford,M.S., Martin,E.P., … SPIE-The International Society for Optical Engineering
6 国際会議録 Characterization of gate electrode etch process for 0.25 ｦﾌm extended to 0.18 ｦﾌm Gerung,H., Chhagan,V.K., Yelehanka,P.R., Zhou,M.S., Hui,J.K.L. SPIE - The International Society for Optical Engineering	12 国際会議録 Illumination condition and mask bias for 0.15-ｦﾌm pattern with KrF and ArF lithography Tabuchi,H., Shichijo,Y., Oka,N., Takenaka,N., lguchi,K. SPIE - The International Society for Optical Engineering

1

2

3

4

5

6

7

8

9

10

11

12