Blank Cover Image

Drain profile engineering for MOSFET devices with channel lengths below 100 nm

著者名:
Saha,S.K. ( VLSI Technology,Inc )  
掲載資料名:
Microelectronic Device Technology III
シリーズ名:
Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号:
3881
発行年:
1999
開始ページ:
195
終了ページ:
204
出版情報:
Bellingham, Wash.: SPIE - The International Society for Optical Engineering
ISSN:
0277786X
ISBN:
9780819434784 [0819434787]
言語:
英語
請求記号:
P63600/3881
資料種別:
国際会議録

類似資料:

1 国際会議録 Effect of Channel Profile Engineering on Hot Carrier Reliability in nMOSFETs With 100 nm Channel Lengths

Saha, Samar K.

MRS - Materials Research Society
7 国際会議録 Drain Engineering of Sub-Quarter-μm MOSFET Devices

Tsai, J.-Y., Osburn, C.M.

Electrochemical Society
2 国際会議録 Scaling considerations for MOSFET devices with 25-nm channel lengths

Saga,S.K.

SPIE-The International Society for Optical Engineering
8 国際会議録 Device characteristics of sub-20-nm silicon nanotransistors

Saha, S.

SPIE-The International Society for Optical Engineering
3 国際会議録 Optimization and Realization of Sub 100nm Channel Length Lateral Asymmetric Channel P-MOSFETS

Hemkar,M., Vasi,J., Rao,V.Ramgopal, Cheng,B., Woo,J.C.S.

SPIE - The International Society for Optical Engineering
9 国際会議録 Performance Trade-offs by the use of High-K Gate Dielectrics in Sub 100 nm Channel Length MOSFETs

Sharma,Sharad, Rao,V.Ramgopal

SPIE - The International Society for Optical Engineering
4 国際会議録 Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET

Kim, J.-H., Kim, G.-H., Ko, S.-W., Jung, H.-K.

SPIE-The International Society for Optical Engineering
10 国際会議録 Computation of Effective Mobility in Buried Channel Heterostructure MOSFET

Kar, G.S., Maikap, S., Ray, S.K., Chakrabarti, N.B.

SPIE-The International Society for Optical Engineering
5 国際会議録 Enhanced Short-Channel Effects of Sub-50 nm Gate Length MOSFETs with High-k Gate Insulator Films

Fujimura, R., Takeda, M., Sato, K., Ohmi, S.-I., Ishiwara, H., Iwai, H.

Electrochemical Society
11 国際会議録 Performance Evaluation of 15nm Gate Length Double-Gate n-MOSFETs with High Mobility Channels: III-V, Ge and Si

D. Kim, T. Krishnamohan, K. Saraswat

Electrochemical Society
6 国際会議録 (6.3) 11:35 - 11:55 AM - Schottky Barrier Height Engineering with a Strained-Si channel for Sub-50nm Gate Schottky Source/Drain MOSFETs

Ikeda, K., Yamashita, Y., Endoh, A., Hikosaka, K., Mimura, T. (Fujitsu)

Electrochemical Society
12 国際会議録 100-nm device fabrication using ArF resist

Lee, S.-K., Jung, J.-C., Hwang, Y.-S., Park, K.-D., Kim, J.-S., Kong, K.-K., Shin, K.-S.

SPIE-The International Society for Optical Engineering
1
 
2
 
3
 
4
 
5
 
6
 
7
 
8
 
9
 
10
 
11
 
12