Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement

Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement

Author(s):

Publication title:

SiGe and Ge, materials, processing, and devices

Title of ser.:

ECS transactions

Ser. no.:

3(7)

Pub. Year:

2006

Page(from):

399

Page(to):

410

Pages:

12

Pub. info.:

Pennington, N.J.: Electrochemical Society

ISSN:

19385862

ISBN:

9781566775076 [1566775078]

Language:

English

Call no.:

E23400/3-7

Type:

Conference Proceedings

Details

TDL ID:	ZA00047115
Series ID:	PA00000034
Conf. info. (Name):	SiGe and Ge Materials, Processing, and Devices Symposium ; Joint International Electrochemical Society Meeting ; Meeting of the Electrochemical Society ; Congreso de la Sociedad Mexicana de Electroquimica
Conf. info. (Number):	2nd ; 2006 ; 210th ; 21st
Conf. info. (Venue):	Cancun, Mexico
Conf. info. (Date):	2006.10.29-2006.11.03
Note for article:	210th ECS Meeting, October 29-November 3, 2006, Cancun, Mexico

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