Optimization of interconnection layout for multitransistor cell shrinkability

Optimization of interconnection layout for multitransistor cell shrinkability

Author(s):

Banachowicz, B. ( Cypress Semiconductor Corp. (USA) )
Pohland, O. ( Cypress Semiconductor Corp. (USA) )
Balasinski, A. ( Cypress Semiconductor Corp. (USA) )

Publication title:

Design and process integration for microelectronic manufacturing II [sic] : 26-27 February 2004, Santa Clara, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

5379

Pub. Year:

2004

Page(from):

235

Page(to):

240

Pages:

6

Pub. info.:

Bellingham, Wash., USA: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819452924 [0819452920]

Language:

English

Call no.:

P63600/5379

Type:

Conference Proceedings

Details

TDL ID:	ZA00013731
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Design and process integration for microelectronic manufacturing
Conf. info. (Number):	2004 : 2nd
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	2004.02.26-2004.02.27

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