Device Challenges for Sub-150 nm CMOS*

Device Challenges for Sub-150 nm CMOS*

Author(s):: Woo, J.C.S.
Publication title:: ULSI Process Integration : proceedings of the International Symposium
Title of ser.:: Electrochemical Society Proceedings Series
Ser. no.:: 2001-2
Pub. Year:: 2001
Page(from):: 489
Page(to):: 494
Pages:: 6
Pub. info.:: Pennington, N.J.: Electrochemical Society
ISSN:: 01616374
ISBN:: 9781566773089 [1566773083]
Language:: English
Call no.:: E23400/2001-2
Type:: Conference Proceedings

Details

TDL ID:	ZA00014006
Series ID:	PA00000028
Conf. info. (Name):	International Symposium on ULSI Process Integration ; Meeting of the Electrochemical Society
Conf. info. (Number):	2nd ; 199th
Conf. info. (Venue):	Washington, D.C., USA
Conf. info. (Date):	2001.03.24-2001.03.31

Similar Items:

1 Conference Proceedings Optimization and Realization of Sub 100nm Channel Length Lateral Asymmetric Channel P-MOSFETS Hemkar,M., Vasi,J., Rao,V.Ramgopal, Cheng,B., Woo,J.C.S. SPIE - The International Society for Optical Engineering	7 Conference Proceedings Heavy Ion Induced Upset Cross-Sections of 150nm SOI CMOS SRAMs Fabricated in UNIBOND M. S. Liu, D. K. Nelson, J. C. Tsang, H. L. Hughes Electrochemical Society
2 Conference Proceedings Digital CMOS active pixel image sensor for multimedia applications Zhou,Z., Pain,B., Woo,J.C.S., Fossum,E.R. SPIE-The International Society for Optical Engineering	8 Conference Proceedings Cost-effective pattern inspection system using Xe-Hg lamp in challenge of sub-65-nm node W. S. Kim, J. H. Park, D. -H. Chung, S. -G. Woo SPIE - The International Society of Optical Engineering
3 Conference Proceedings X-ray exposure in the manufacture of sub-150-nm gate lines Lamberti,A.C., Agnello,P.D., Crabbe,E.F., Guardia,R.Della, Oberschmidt,J.M., Subbana,S., Wu,S. SPIE-The International Society for Optical Engineering	9 Conference Proceedings Successful application of angular scatterometry to process control in sub-100-nm DRAM device Kim, J.-, Kim, S.-J., Chin, S.-B., Oh, S.-H., Goo, D.-H., Lee, S.-J., Woo, S.-G., Cho, H.-K., Han, W.-S., Moon, J.-T., … SPIE - The International Society of Optical Engineering
4 Conference Proceedings Nickel SALICIDE Technology for Sub-100 nm CMOS Devices Lu, J.P., Miles, D., Li-Fatou, A., Xu, Y.Q., Zhao, J., Gurba, A., Griffin, A., Jr., Hornug, B., Hewson, M., Grider, T., … Electrochemical Society	10 Conference Proceedings Implementation of the ArF resists based on VEMA for sub-100-nm device Kim, H.-W., Lee, S., Choi, S.-J., Lee, S.-H., Kang, Y., Woo, S.-G., Nam, D.S., Chae, Y.-S., Kim, J.S., Moon, J.-T., … SPIE-The International Society for Optical Engineering
5 Conference Proceedings New PEC optimization for the mask fabrication of sub-50nm memory device S. Lee, D. Ryu, J. Park, D. Nam, H. Kim, B. Kim, S. Woo, H. Cho SPIE - The International Society of Optical Engineering	11 Conference Proceedings A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18ｦﾌm CMOS Devices Ren, L. P., Liu, P., Pan, G. Z., Woo, Jason C. S. MRS - Materials Research Society
6 Conference Proceedings Strategy for sub-80-nm contact hole patterning considering device fabrication Yoon, J.-Y., Hata, M., Hah, J.-H., Kim, H.-W., Woo, S.-G., Cho, H.-K., Han, W.-S. SPIE - The International Society of Optical Engineering	12 Conference Proceedings A Novel Low-Temperature Self-Aligned Ti Silicide Technology for Sub-0.18 ｦﾌm CMOS Devices Ren, L. P., Liu, P., Pan, G. Z., Woo, Jason C. S. MRS - Materials Research Society

1

2

3

4

5

6

7

8

9

10

11

12