Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

Author(s):

K.-K. Lin ( Chartered Semiconductor Manufacturing, Inc., USA )
B. P. Wong ( Chartered Semiconductor Manufacturing, Inc., USA )
F. A. J. M. Driessen ( Takumi Technology Corp., USA )
E. Morita ( Takumi Technology Corp., USA )
S. Klaver ( Takumi Technology Corp., USA )

Publication title:

Photomask technology 2007

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6730

Pub. Year:

2007

Vol.:

1

Page(from):

67300X-1

Page(to):

67300X-9

Pages:

9

Pub. info.:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819468871 [0819468878]

Language:

English

Call no.:

P63600/6730

Type:

Conference Proceedings

Details

TDL ID:	ZA00052371
Series ID:	PA00000029
Conf. info. (Name):	SPIE Photomask Technology : Photomask Technology 2007
Conf. info. (Number):	2007
Conf. info. (Venue):	Monterey, California, USA
Conf. info. (Date):	2007.09.18-2007.09.21
Note for article:	Photomask technology 2007, 18-21 September 2007, Monterey, California, USA - Session 8. DFM 3: Modal aware design and optimization (6730-33)

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