Immersion resist process for 32-nm node logic devices

Immersion resist process for 32-nm node logic devices

Author(s):

T. Ema ( Toshiba Corp., Japan )
K. Sho ( Toshiba Corp., Japan )
H. Yonemitsu ( Toshiba Corp., Japan )
Y. Seino ( Toshiba Corp., Japan )
H. Fujise ( Toshiba Corp., Japan )

Publication title:

Advances in resist materials and processing technology XXV

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6923

Pub. Year:

2008

Vol.:

1

Page(from):

69230E-1

Page(to):

69230E-12

Pages:

12

Pub. info.:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819471086 [0819471089]

Language:

English

Call no.:

P63600/6923

Type:

Conference Proceedings

Details

TDL ID:	ZA00052554
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Advances in Resist Materials and Processing Technology
Conf. info. (Number):	2008 : 25th
Conf. info. (Venue):	San Jose, California, USA
Conf. info. (Date):	2008.02.25-2008.02.27
Note for article:	Advances in resist materials and processing technology XXV, 25-27 February 2008, San Jose, California, USA. Session 3. Materials and Processes for Immersion Lithography II, 69230E, 6923-13

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