Evaluation of immersion lithography processes for 55-nm node logic devices

Evaluation of immersion lithography processes for 55-nm node logic devices

Author(s):

T. Nakata ( NEC Electronics Corp. (Japan) )
T. Kodama ( NEC Electronics Corp. (Japan) )
M. Komori ( NEC Electronics Corp. (Japan) )
N. Onoda ( NEC Electronics Corp. (Japan) )
T. Uchiyama ( NEC Electronics Corp. (Japan) )

Publication title:

Advances in resist materials and processing technology XXIV

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6519

Pub. Year:

2007

Pub. info.:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819466389 [0819466387]

Language:

English

Call no.:

P63600/6519

Type:

Conference Proceedings

Details

TDL ID:	ZA00046826
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Advances in Resist Materials and Processing Technology
Conf. info. (Number):	2007 : 24th
Conf. info. (Venue):	San Jose, CA, USA
Conf. info. (Date):	2007.02.26-2007.02.28

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