Planar Bonded Double Gate MOS Transistors Down to LG = 10 nm (Invited paper)

Planar Bonded Double Gate MOS Transistors Down to LG = 10 nm (Invited paper)

Author(s):

Vinet, M.

Publication title:

ULSI Process Integration : proceedings of the International Symposium

Title of ser.:

Electrochemical Society Proceedings Series

Ser. no.:

2005-06

Pub. Year:

2005

Page(from):

285

Page(to):

295

Pages:

11

Pub. info.:

Pennington, N.J.: Electrochemical Society

ISSN:

01616374

ISBN:

9781566774642 [1566774640]

Language:

English

Call no.:

E23400/200506

Type:

Conference Proceedings

Details

TDL ID:	ZA00015389
Series ID:	PA00000028
Conf. info. (Name):	International Symposium on ULSI Process Integration ; Meeting of the Electrochemical Society
Conf. info. (Number):	4th ; 207th
Conf. info. (Venue):	Quebec, Canada
Conf. info. (Date):	2005.05.16-2005.05.20

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