61 Impact of Recessed S/D SiGe Integration Parameters on Device Performance

61 Impact of Recessed S/D SiGe Integration Parameters on Device Performance

Author(s):

Washington, L.

Publication title:

Advanced gate stack, source/drain and channel engineering for Si-based CMOS, new materials, processes, and equipment : proceedings of the international symposium

Title of ser.:

Electrochemical Society Proceedings Series

Ser. no.:

2005-05

Pub. Year:

2005

Page(from):

515

Page(to):

522

Pages:

8

Pub. info.:

Pennington, NJ: Electrochemical Society

ISSN:

01616374

ISBN:

9781566774635 [1566774632]

Language:

English

Call no.:

E23400/200505

Type:

Conference Proceedings

Details

TDL ID:	ZA00015388
Series ID:	PA00000028
Conf. info. (Name):	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS ; Meeting of the Electrochemical Society
Conf. info. (Number):	2005 ; 207th
Conf. info. (Venue):	Quebec City, QC, Canada
Conf. info. (Date):	2005.05.16-2005.05.18

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