Combining OPC and design for printability into 65-nm logic designs

Combining OPC and design for printability into 65-nm logic designs

Author(s):

Lucas, K.D. ( Motorola (France) )

Yuan, C.-M. ( Motorola (USA) )

Boone, R. ( Motorola (France) )

Strozewski, K. ( Motorola (USA) )

Porter, J. ( Motorola (USA) )

Tian, R. ( Motorola (USA) )

Wimmer, K. ( Motorola (France) )

Cobb, J. ( Motorola (USA) )

Wilkinson, B. ( Motorola (USA) )

Toublan, O. ( Mentor Graphics Europe (France) )

5 more

Publication title:

Design and process integration for microelectronic manufacturing II [sic] : 26-27 February 2004, Santa Clara, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

5379

Pub. Year:

2004

Page(from):

158

Page(to):

169

Pages:

12

Pub. info.:

Bellingham, Wash., USA: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819452924 [0819452920]

Language:

English

Call no.:

P63600/5379

Type:

Conference Proceedings

Details

TDL ID:	ZA00013731
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Design and process integration for microelectronic manufacturing
Conf. info. (Number):	2004 : 2nd
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	2004.02.26-2004.02.27

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