Assessing technology options for 65-nm logic circuits

Assessing technology options for 65-nm logic circuits

Author(s):

Pramanik, D. ( Synopsys, Inc. (USA) )
Cote, M.L. ( Synopsys, Inc. (USA) )
Beaudette, K. ( Synopsys, Inc. (USA) )
Axelrad, V. ( Sequoia Design Systems, Inc. (USA) )

Publication title:

Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

5042

Pub. Year:

2003

Page(from):

30

Page(to):

41

Pages:

12

Pub. info.:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819448477 [0819448478]

Language:

English

Call no.:

P63600/5042

Type:

Conference Proceedings

Details

TDL ID:	ZA00013033
Series ID:	PA00000029
Conf. info. (Name):	Microelectronic Manufacturing : Design and process integration for microelectronic manufacturing
Conf. info. (Number):	2003 : 2nd
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	2003.02.26-2003.02.28

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