100-nm CMOS gates patterned with 3ｦﾒbelow 10 nm

100-nm CMOS gates patterned with 3ｦﾒbelow 10 nm

Author(s):

Liu,H.Y. ( Hewlett-Packard Labs. )

Diaz,C.H. ( Hewlett-Packard Labs. )

Chi,C. ( Hewlett-Packard Labs. )

Kavari,R. ( Hewlett-Packard Labs. )

Cheng,P. ( Intel Corp. )

Cao,M. ( Hewlett-Packard Labs. )

Gleason,R.E. ( Hewlett-Packard Labs. )

Doyle,B.S. ( Intel Corp. )

Greene,W. ( Hewlett-Packard Labs. )

Ray,G. ( Hewlett-Packard Labs. )

5 more

Publication title:

Emerging lithographic technologies II : 23-25 February 1998, Santa Clara, California

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

3331

Pub. Year:

1998

Page(from):

375

Page(to):

381

Pub. info.:

Bellingham, Wash., USA: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819427762 [0819427764]

Language:

English

Call no.:

P63600/3331

Type:

Conference Proceedings

Details

TDL ID:	ZA00019241
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Emerging Lithographic Technologies
Conf. info. (Number):	1998 : 2nd
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	1998.02.23-1998.02.25

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