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Scalability of conventional and sidewall-sealed LOCOS technology for 256-Mbit DRAM array and periphery isolation

Author(s):
Publication title:
Microelectronic Device and Multilevel Interconnection Technology II
Title of ser.:
Proceedings of SPIE - the International Society for Optical Engineering
Ser. no.:
2875
Pub. Year:
1996
Page(from):
236
Page(to):
243
Pub. info.:
Bellingham, Wash.: SPIE-The International Society for Optical Engineering
ISSN:
0277786X
ISBN:
9780819422736 [0819422738]
Language:
English
Call no.:
P63600/2875
Type:
Conference Proceedings

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