Lg=0.25-ｦﾌm CMOS devices with N+polycide gate for 3.3-V application

Lg=0.25-ｦﾌm CMOS devices with N+polycide gate for 3.3-V application

Author(s):

Choi,J.Y. ( Integrated Device Technology )
Ma,Z.

Publication title:

Microelectronic Device and Multilevel Interconnection Technology II

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

2875

Pub. Year:

1996

Page(from):

164

Page(to):

168

Pub. info.:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819422736 [0819422738]

Language:

English

Call no.:

P63600/2875

Type:

Conference Proceedings

Details

TDL ID:	ZA00018883
Series ID:	PA00000029
Conf. info. (Name):	Microelectronic Manufacturing : Microelectronic Device and Multilevel Interconnection Technology
Conf. info. (Number):	1996 : 2nd
Conf. info. (Venue):	Austin, TX, USA
Conf. info. (Date):	1996.10.16-1996.10.17

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