Optimization of Dual Poly Gate Low Voltage CMOS Process

Optimization of Dual Poly Gate Low Voltage CMOS Process

Author(s):

Publication title:

Proceedings of the Tenth International Workshop on the Physics of Semiconductor Devices (December 14-18, 1999)

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

3975

Pub. Year:

2000

Vol.:

Part2

Page(from):

871

Page(to):

874

Pub. info.:

Bellingham, Wash.: SPIE - The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819436016 [0819436011]

Language:

English

Call no.:

P63600/3975

Type:

Conference Proceedings

Details

TDL ID:	ZA00017117
Series ID:	PA00000029
Conf. info. (Name):	International Workshop on the Physics of Semiconductor Devices
Conf. info. (Number):	1999 : 10th
Conf. info. (Venue):	Delhi, India
Conf. info. (Date):	1999.12.14-1999.12.18

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