Process optimization by reducing I-D bias for 0.25-ｦﾌm logic devices

Process optimization by reducing I-D bias for 0.25-ｦﾌm logic devices

Author(s):

Park,K.-Y. ( Hyundai Electronics Industries Co.,Ltd. )
Choi,B.-I.
Lee,W.-G.
Ko,C.-G.

Publication title:

Optical Microlithography X

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

3051

Pub. Year:

1997

Page(from):

170

Page(to):

181

Pub. info.:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819424655 [081942465X]

Language:

English

Call no.:

P63600/3051

Type:

Conference Proceedings

Details

TDL ID:	ZA00016573
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Optical Microlithography
Conf. info. (Number):	1997 : 10th
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	1997.03.12-1997.03.14

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