Methodologies for Placement Floorplanning and Clustering in VLSI Design.

Methodologies for Placement Floorplanning and Clustering in VLSI Design.

著者名:

掲載資料名:

S.M.E. technical paper

シリーズ名:

SME Technical Paper : TP

シリーズ巻号:

2007

発行年:

2007

通号:

TP07PUB014

ペーパー番号:

TP07PUB014

総ページ数:

18

出版情報:

Dearborn, Mich.: Society of Manufacturing Engineers

言語:

英語

請求記号:

S42600

資料種別:

テクニカルペーパー

詳細

TDL書誌ID:	ZA00052158
シリーズID:	PA00000134

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