Impact of gate line edge roughness on double-gate FinFET performance variability

Impact of gate line edge roughness on double-gate FinFET performance variability

著者名:

K. Patel ( SanDisk Inc., USA )
T.-J. King Liu ( Univ. of California, Berkeley, USA )
C. Spanos ( Univ. of California, Berkeley, USA )

掲載資料名:

Design for manufacturability through design-process integration II : 28-29 February 2008, San Jose, California, USA

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

6925

発行年:

2008

開始ページ:

69251I-1

終了ページ:

69251I-10

総ページ数:

10

出版情報:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819471109 [0819471100]

言語:

英語

請求記号:

P63600/6925

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00052556
シリーズID:	PA00000029
会議名:	SPIE Advanced Lithography : Design for Manufacturability through Design-Process Integration
回次:	2008 : 2nd
会議開催地:	San Jose, California, USA
会議開催年:	2008.02.28-2008.02.29
論文注記:	Design for manufacturability through design-process integration II, 28-29 February 2008, San Jose, California, USA. Poster Session, 69251I, 6925-52

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