Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

著者名:

K.-K. Lin ( Chartered Semiconductor Manufacturing, Inc., USA )
B. P. Wong ( Chartered Semiconductor Manufacturing, Inc., USA )
F. A. J. M. Driessen ( Takumi Technology Corp., USA )
E. Morita ( Takumi Technology Corp., USA )
S. Klaver ( Takumi Technology Corp., USA )

掲載資料名:

Photomask technology 2007

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

6730

発行年:

2007

巻:

1

開始ページ:

67300X-1

終了ページ:

67300X-9

総ページ数:

9

出版情報:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819468871 [0819468878]

言語:

英語

請求記号:

P63600/6730

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00052371
シリーズID:	PA00000029
会議名:	SPIE Photomask Technology : Photomask Technology 2007
回次:	2007
会議開催地:	Monterey, California, USA
会議開催年:	2007.09.18-2007.09.21
論文注記:	Photomask technology 2007, 18-21 September 2007, Monterey, California, USA - Session 8. DFM 3: Modal aware design and optimization (6730-33)

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