Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation

Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation

著者名:

掲載資料名:

Transistor scaling--methods, materials and modeling : symposium held April 18-19, 2006, San Francisco, California, U.S.A.

シリーズ名:

Materials Research Society symposium proceedings

シリーズ巻号:

913

発行年:

2006

開始ページ:

39

終了ページ:

48

総ページ数:

10

出版情報:

Warrendale, Pa.: Materials Research Society

ISSN:

02729172

ISBN:

9781558998698 [1558998691]

言語:

英語

請求記号:

M23500/913

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00046617
シリーズID:	PA00000011
会議名:	MRS Spring Meeting : Symposium D
回次:	2006
会議開催地:	San Francisco, California, USA
会議開催年:	2006.04.18-2006.04.19

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