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DFM: a practical layout optimization procedure for the improved process window for an existing 90-nm product [6156-11]

著者名:
Ho, J. ( Xilinx Inc. (USA) )
Wang, Y. ( Xilinx Inc. (USA) )
Hou, Y.-C. ( United Microelectronics Corp. (Taiwan) )
Lin, B. S.-M. ( United Microelectronics Corp. (Taiwan) )
Yu, C. C. ( United Microelectronics Corp. (Taiwan) )
Wu, K. ( Anchor Semiconductor, Inc. (USA) )
Ma, C. ( KLA-Tencor Inc. (USA) )
さらに 2 件
掲載資料名:
Design and process integration for microelectronic manufacturing IV : 23-24 February, 2006, San Jose, California, USA
シリーズ名:
Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号:
6156
発行年:
2006
開始ページ:
61560C
出版情報:
Bellingham, Wash.: SPIE - The International Society of Optical Engineering
ISSN:
0277786X
ISBN:
9780819461995 [0819461997]
言語:
英語
請求記号:
P63600/6156
資料種別:
国際会議録

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