Gate-leakage-tolerant circuits in deep sub-100-nm CMOS technologies

Gate-leakage-tolerant circuits in deep sub-100-nm CMOS technologies

著者名:

Kang, S.-M. ( Univ. of California/Santa Cruz (USA) )
Yang, G. ( Univ. of California/Santa Cruz (USA) )
Wang, Z. ( Univ. of California/Santa Cruz (USA) )

掲載資料名:

Microelectronics: Design, Technology, and Packaging

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5274

発行年:

2004

開始ページ:

56

終了ページ:

66

総ページ数:

11

出版情報:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819451675 [0819451673]

言語:

英語

請求記号:

P63600/5274

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00013616
シリーズID:	PA00000029
会議名:	Smart Materials, Nano-, and Micro- Smart Systems : Microelectronics
回次:	2003
会議開催地:	Perth, Australia
会議開催年:	2003.12.10-2003.12.12

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