Optimizing manufacturability for the 65-nm process node

Optimizing manufacturability for the 65-nm process node

著者名:

Pramanik, D. ( Synopsys, Inc. (USA) )
Cote, M.L. ( Synopsys, Inc. (USA) )

掲載資料名:

Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

5042

発行年:

2003

開始ページ:

326

終了ページ:

333

総ページ数:

8

出版情報:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819448477 [0819448478]

言語:

英語

請求記号:

P63600/5042

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00013033
シリーズID:	PA00000029
会議名:	Microelectronic Manufacturing : Design and process integration for microelectronic manufacturing
回次:	2003 : 2nd
会議開催地:	Santa Clara, CA, USA
会議開催年:	2003.02.26-2003.02.28

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