Blank Cover Image

Resolution enhancement technology requirements for 65-nm node

著者名:
  • Kroyan, A. ( Numerical Technologies, Inc. (USA) )
  • Liu, H. ( Numerical Technologies, Inc. (USA) )
掲載資料名:
Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA
シリーズ名:
Proceedings of SPIE - the International Society for Optical Engineering
シリーズ巻号:
5042
発行年:
2003
開始ページ:
305
終了ページ:
313
総ページ数:
9
出版情報:
Bellingham, Wash.: SPIE-The International Society for Optical Engineering
ISSN:
0277786X
ISBN:
9780819448477 [0819448478]
言語:
英語
請求記号:
P63600/5042
資料種別:
国際会議録

類似資料:

1 国際会議録 Effects of alternating aperture PSM design on image imbalance for 65-nm technology

Kroyan, A., Liu, H.-Y.

SPIE-The International Society for Optical Engineering
7 国際会議録 Silicides for the 65 nm Technology Node

Besser, Payk R., Chan, Simon, Paton, Eric, Kammler, Thorsten, Brown, David, King, Paul, Pressley, Laura

Materials Research Society
2 国際会議録 Image-blur tolerances for 65-nm and 45-nm node IC manufacturing

Lalovic, I., Kroyan, A., Kye, J., Liu, H.-Y., Levinson, H.J.

SPIE-The International Society for Optical Engineering
8 国際会議録 Technology qualification for 65-nm node

Jacek K. Tyminski, Toshiharu Nakashima

SPIE - The International Society of Optical Engineering
3 国際会議録 Resolution enhancement technology for ArF dry lithography at 65 nm node

S. Goo, Y. Li

Society of Photo-optical Instrumentation Engineers
9 国際会議録 Measurement precision of CD-SEM for 65-nm technology node

Abe, H., Motoki, H., Ikeda, T., Yamazaki, Y.

SPIE - The International Society of Optical Engineering
4 国際会議録 Resolution enhancement techniques in 65 nm node nested-hole patterning

H. Lee, J. Choi, J. Kim, J.-W. Han, K.-Y. Kim

Society of Photo-optical Instrumentation Engineers
10 国際会議録 EPL performance in 65-nm node metallization technology and beyond

Kakutani, Y., Niibe, M., Takase, H., Terashima, S., Kondo, H., Matsunari, S., Aoki, T., Gomei, Y., Fukuda, Y.

SPIE - The International Society of Optical Engineering
5 国際会議録 Illumination optimization for 65nm technology node [6349-188]

Wang, C.-H., Liu, Q., Zhang, L., Hung, C.-Y.

SPIE - The International Society of Optical Engineering
11 国際会議録 High-performance circuit design for the RET-enabled 65-nm technology node

Liebmann, L.W., Barish, A.E., Baum, Z., Bonges, H.A., Bukofsky, S.J., Fonseca, C.A., Halle, S.D., Northrop, G.A., …

SPIE - The International Society of Optical Engineering
6 国際会議録 Taking the X Architecture to the 65-nm technology node

Sarma, R.C., Smayling, M.C., Arora, N., Nagata, T., Duane, M.P., Shah, S., Keston, H.J., Oemardani, S.

SPIE - The International Society of Optical Engineering
12 国際会議録 Advanced method to monitor design-process marginality for 65nm node and beyond

C. Huang, C. Young, H. Liu, S. F. Tzou, D. Tsui

Society of Photo-optical Instrumentation Engineers
1
 
2
 
3
 
4
 
5
 
6
 
7
 
8
 
9
 
10
 
11
 
12