Advanced procedure to evaluate process performance at very low k1 based on device parameters linked to lithography and process data: ？. Verification of cell layout based on integration of optical and electrical simulations

Advanced procedure to evaluate process performance at very low k1 based on device parameters linked to lithography and process data: ？. Verification of cell layout based on integration of optical and electrical simulations

著者名:

Balasinski,A. ( Cypress Semiconductor )
Iandolo,W.
Joshi,D.
Karklin,L.
Axelrad,V.

掲載資料名:

Optical Microlithography XIV

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

4346

発行年:

2001

巻:

4346

パート:

Two of Two Parts

開始ページ:

1514

終了ページ:

1521

総ページ数:

8

出版情報:

Bellingham, Wash.: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819440327 [0819440329]

言語:

英語

請求記号:

P63600/4346

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00012062
シリーズID:	PA00000029
会議名:	SPIE Advanced Lithography : Optical microlithography
回次:	2001 : 14th
会議開催地:	Santa Clara, CA, USA
会議開催年:	2001.02.27-2001.03.02

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