Optimized shallow trench isolation for sub-0.18-ｦﾌm ASIC technologies

Optimized shallow trench isolation for sub-0.18-ｦﾌm ASIC technologies

著者名:

Nouri,F. ( VLSI Technology,Inc. )

Laparra,O. ( VLSI Technology,Inc. )

Sur,H. ( VLSI Technology,Inc. )

Saha,S. ( VLSI Technology,Inc. )

Pramanik,D. ( VLSI Technology,Inc. )

Manley,M. ( VLSI Technology,Inc. )

さらに 1 件

掲載資料名:

Microelectronic device technology II : 23-24 September, 1998, Santa Clara, California

シリーズ名:

Proceedings of SPIE - the International Society for Optical Engineering

シリーズ巻号:

3506

発行年:

1998

開始ページ:

156

終了ページ:

166

出版情報:

Bellingham, Washington: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819429650 [0819429651]

言語:

英語

請求記号:

P63600/3506

資料種別:

国際会議録

詳細

TDL書誌ID:	ZA00016438
シリーズID:	PA00000029
会議名:	Microelectronic Manufacturing : Microelectronic device technology
回次:	1998 : 2nd
会議開催地:	Santa Clara, CA, USA
会議開催年:	1998.09.23-1998.09.24

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