The Influence of Gate Material, SiO2 Fabrication Method and Gate Edge Effect on Interface Trap Density in 3C-SiC MOS Capacitors

The Influence of Gate Material, SiO₂ Fabrication Method and Gate Edge Effect on Interface Trap Density in 3C-SiC MOS Capacitors

Author(s):

Publication title:

HeteroSiC & WASMPE 2011 : selected, peer reviewed papers from the 4th Workshop on Advanced Semiconductor Materials and Devices for Power Electronics Applications (HeteroSiC & WASMPE 2011), June 27-30, 2011, Tours, France

Title of ser.:

Materials science forum

Ser. no.:

711

Pub. Year:

2012

Page(from):

109

Page(to):

113

Pages:

5

Pub. info.:

Aedermannsdorf, Switzerland: Trans Tech Publications

ISSN:

02555476

Language:

English

Call no.:

M23650

Type:

Conference Proceedings

Details

TDL ID:	ZA00054202
Series ID:	PA00000012
Conf. info. (Name):	Workshop on Advanced Semiconductor Materials and Devices for Power Electronics Applications (HeteroSiC & WASMPE 2011)
Conf. info. (Number):	4th
Conf. info. (Venue):	Tours, France
Conf. info. (Date):	2011.06.27-2011.06.30
Note for article:	4th Workshop on Advanced Semiconductor Materials and Devices for Power Electronics Applications (HeteroSiC & WASMPE 2011), June 27-30, 2011, Tours, France

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