Impact of gate line edge roughness on double-gate FinFET performance variability

Impact of gate line edge roughness on double-gate FinFET performance variability

Author(s):

K. Patel ( SanDisk Inc., USA )
T.-J. King Liu ( Univ. of California, Berkeley, USA )
C. Spanos ( Univ. of California, Berkeley, USA )

Publication title:

Design for manufacturability through design-process integration II : 28-29 February 2008, San Jose, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6925

Pub. Year:

2008

Page(from):

69251I-1

Page(to):

69251I-10

Pages:

10

Pub. info.:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819471109 [0819471100]

Language:

English

Call no.:

P63600/6925

Type:

Conference Proceedings

Details

TDL ID:	ZA00052556
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Design for Manufacturability through Design-Process Integration
Conf. info. (Number):	2008 : 2nd
Conf. info. (Venue):	San Jose, California, USA
Conf. info. (Date):	2008.02.28-2008.02.29
Note for article:	Design for manufacturability through design-process integration II, 28-29 February 2008, San Jose, California, USA. Poster Session, 69251I, 6925-52

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