Study of ELS technology for random logic LSI toward 32-nm node

Study of ELS technology for random logic LSI toward 32-nm node

Author(s):

Y. Setta ( Fujitsu, Ltd., Japan )
K. Morishita ( Fujitsu VLSI, Ltd., Japan )
K. Kobayashi ( Fujitsu, Ltd., Japan )
T. Chijimatsu ( Fujitsu, Ltd., Japan )
S. Asai ( Fujitsu, Ltd., Japan )

Publication title:

Optical Microlithography XXI

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6924

Pub. Year:

2008

Vol.:

2

Page(from):

692423-1

Page(to):

692423-8

Pages:

8

Pub. info.:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819471093 [0819471097]

Language:

English

Call no.:

P63600/6924

Type:

Conference Proceedings

Details

TDL ID:	ZA00052555
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Optical Microlithography
Conf. info. (Number):	2008 : 21st
Conf. info. (Venue):	San Jose, California, USA
Conf. info. (Date):	2008.02.26-2008.02.29
Note for article:	Optical Microlithography XXI, 26-29 February 2008, San Jose, California, USA. Poster Session: Double Masking, 692423, 6924-74

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