Process control for 45 nm CMOS logic gate patterning

Process control for 45 nm CMOS logic gate patterning

Author(s):

B. Le Gratiet ( STMicroelectronics, France )
P. Gouraud ( STMicroelectronics, France )
E. Aparicio ( STMicroelectronics, France )
L. Babaud ( STMicroelectronics, France )
K. Dabertrand ( STMicroelectronics, France )

Publication title:

Metrology, inspection, and process control for microlithography XXII

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6922

Pub. Year:

2008

Vol.:

1

Page(from):

69220Z-1

Page(to):

69220Z-11

Pages:

11

Pub. info.:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819471079 [0819471070]

Language:

English

Call no.:

P63600/6922

Type:

Conference Proceedings

Details

TDL ID:	ZA00052553
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Metrology, Inspection, and Process Control for Microlithography
Conf. info. (Number):	2008 : 22nd
Conf. info. (Venue):	San Jose, California, USA
Conf. info. (Date):	2008.02.25-2008.02.28
Note for article:	Metrology, inspection, and process control for microlithography XXII, San Jose, California, USA, 25-28 February 2008 - Session 7. Process Control (69220Z/6922-33)

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