A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL

A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL

Author(s):

K. Vitoroulis ( Concordia Univ., Canada )
T. Obuchowicz ( Concordia Univ., Canada )
A. J. Al-Khalili ( Concordia Univ., Canada )

Publication title:

Microelectronics : design, technology, and packaging III : 5-7 December 2007, Canberra, Australia

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6798

Pub. Year:

2008

Page(from):

67980Q-1

Page(to):

67980Q-12

Pages:

12

Pub. info.:

Bellingham, Wash.: Society of Photo-optical Instrumentation Engineers

ISSN:

0277786X

ISBN:

9780819469694 [0819469696]

Language:

English

Call no.:

P63600/6798

Type:

Conference Proceedings

Details

TDL ID:	ZA00052429
Series ID:	PA00000029
Conf. info. (Name):	Smart Materials, Nano-, and Micro- Smart Systems : Microelectronics
Conf. info. (Number):	2007 : 3rd
Conf. info. (Venue):	Canberra, Australia
Conf. info. (Date):	2007.12.05-2007.12.07
Note for article:	Microelectronics: Design, Technology, and Packaging III, 5-7 December 2007, Canberra, Australia - Session 6. Modelling and Simulations (6798-25)

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