Prototyping the HPDP Chip on STM 65 NM Process
- Author(s):
- Publication title:
- Proceedings of DASIA 2011 : DAta Systems in Aerospace : 17-20 May 2011, San Anton, Malta
- Title of ser.:
- ESA SP
- Ser. no.:
- 694
- Pub. Year:
- 2011
- Pages:
- 2
- Pub. info.:
- Noordwijk: ESA Communications
- ISSN:
- 1609042X
- ISBN:
- 9789290922582 [9290922583]
- Language:
- English
- Call no.:
- E11690/694
- Type:
- Conference Proceedings
Similar Items:
1
Conference Proceedings
First Experiences with Chip Development on the Commercial STM 65 nm Process
ESA Communications |
SPIE-The International Society for Optical Engineering |
2
Conference Proceedings
Features Relative to the Integration of TA205 as a Gate Dielectric in CMOS Processes
Electrochemical Society |
8
Conference Proceedings
Impact of process variation on 65nm across-chip Iinewidth variation [6156-64]
SPIE - The International Society of Optical Engineering |
3
Conference Proceedings
Finding the needle in the haystack: using full-chip process window analysis to qualify competing SRAF placement strategies for 65 nm [6349-70]
SPIE - The International Society of Optical Engineering |
SPIE - The International Society of Optical Engineering |
SPIE - The International Society of Optical Engineering |
SPIE-The International Society for Optical Engineering |
5
Conference Proceedings
Process, design, and optical proximity correction requirements for the 65-nm device generation
SPIE-The International Society for Optical Engineering |
Electrochemical Society |
6
Conference Proceedings
Process, design and optical proximity correction requirements for the 65nm device generation
SPIE-The International Society for Optical Engineering |
Kluwer Academic Publishers |