3D Wafer Level Packaging: Processes and Materials for Trough Silicon Vias & Thin Die Embedding

3D Wafer Level Packaging: Processes and Materials for Trough Silicon Vias & Thin Die Embedding

Author(s):

Philippe Soussan

Publication title:

Materials and technologies for 3-D integration : symposium held December 1-3, 2008, Boston, Massachusetts, U.S.A.

Title of ser.:

Materials Research Society symposium proceedings

Ser. no.:

1112

Pub. Year:

2009

Page(from):

43

Page(to):

54

Pages:

12

Pub. info.:

Warrendale, Pa.: Materials Research Society

ISSN:

02729172

ISBN:

9781605110844 [1605110841]

Language:

English

Call no.:

M23500/1112

Type:

Conference Proceedings

Details

TDL ID:	ZA00049453
Series ID:	PA00000011
Conf. info. (Name):	MRS Fall Meeting
Conf. info. (Number):	2008
Conf. info. (Venue):	Boston, Massachusetts, USA
Conf. info. (Date):	2008.12.01-2008.12.03

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