Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Author(s):

T. Brist ( Mentor Graphics Corp. (USA) )

L. Hong ( Mentor Graphics Corp. (USA) )

A. Yehia ( Mentor Graphics Corp. (USA) )

T. Tawfik ( Mentor Graphics Corp. (USA) )

S. Shang ( Mentor Graphics Corp. (USA) )

K. Sakajiri ( Mentor Graphics Corp. (USA) )

J. L. Sturtevant ( Mentor Graphics Corp. (USA) )

2 more

Publication title:

Design for manufacturability through design-process integration : 28 February-2 March 2007, San Jose, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6521

Pub. Year:

2007

Pub. info.:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819466402 [0819466409]

Language:

English

Call no.:

P63600/6521

Type:

Conference Proceedings

Details

TDL ID:	ZA00046828
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Design for Manufacturability through Design-Process Integration
Conf. info. (Number):	2007
Conf. info. (Venue):	San Jose, CA, USA
Conf. info. (Date):	2007.02.28-2007.03.02

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