Reticle enhancement verification for the 65nm and 45nm nodes [6156-58]

Reticle enhancement verification for the 65nm and 45nm nodes [6156-58]

Author(s):

Lucas, K. ( Freescale Semiconductor (France) )

Patterson, K. ( Freescale Semiconductor (France) )

Boone, R. ( Freescale Semiconductor (France) )

Miramond, C. ( STMicroelectronics (France) )

Borjon, A. ( Philips Semiconductor (France) )

Belledent, J. ( Philips Semiconductor (France) )

Toublan, O. ( Mentor Graphics Europe (France) )

Entradas, J. ( Mentor Graphics Europe (France) )

Trouiller, Y. ( LETI/CEA (France) )

4 more

Publication title:

Design and process integration for microelectronic manufacturing IV : 23-24 February, 2006, San Jose, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

6156

Pub. Year:

2006

Page(from):

61560R

Pub. info.:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819461995 [0819461997]

Language:

English

Call no.:

P63600/6156

Type:

Conference Proceedings

Details

TDL ID:	ZA00016431
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Design and process integration for microelectronic manufacturing
Conf. info. (Number):	2006 : 4th
Conf. info. (Venue):	San Jose, CA, USA
Conf. info. (Date):	2006.02.23-2006.02.24

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