Improving model-based OPC performance for the 65-nm node through calibration set optimization
- Author(s):
Patterson, K. ( Freescale Semiconductor(France) ) Trouiller, Y. ( CEA-LETI(France) ) Lucas, K. ( Freescale Semiconductor(France) ) Belledent, J. ( Philips Semiconductors(France) ) Borjon, A. ( Philips Semiconductors(France) ) Rody, Y. ( Philips Semiconductors(France) ) Couderc, C. ( Philips Semiconductors(France) ) Sundermann, F. ( STMicroelectronics(France) ) Urbani, J. -C. ( STMicroelectronics(France) ) Baron, S. ( STMicroelectronics(France) ) - Publication title:
- Design and process integration for microelectronic manufacturing III : 3-4 March 2005, San Jose, California, USA
- Title of ser.:
- Proceedings of SPIE - the International Society for Optical Engineering
- Ser. no.:
- 5756
- Pub. Year:
- 2005
- Page(from):
- 294
- Page(to):
- 301
- Pages:
- 8
- Pub. info.:
- Bellingham, Wash.: SPIE - The International Society of Optical Engineering
- ISSN:
- 0277786X
- ISBN:
- 9780819457363 [0819457361]
- Language:
- English
- Call no.:
- P63600/5756
- Type:
- Conference Proceedings
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