Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches

Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches

Author(s):

Kachwala, N. ( Cypress Semiconductor Corp. (USA) )
Iandolo, W. ( Cypress Semiconductor Corp. (USA) )
Brist, T. ( Mentor Graphics Corp. (USA) )
Farnbach, R. ( Mentor Graphics Corp. (USA) )

Publication title:

Design and process integration for microelectronic manufacturing III : 3-4 March 2005, San Jose, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

5756

Pub. Year:

2005

Page(from):

141

Page(to):

149

Pages:

9

Pub. info.:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819457363 [0819457361]

Language:

English

Call no.:

P63600/5756

Type:

Conference Proceedings

Details

TDL ID:	ZA00014983
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Data analysis and modeling for process control
Conf. info. (Number):	2005 : 3rd
Conf. info. (Venue):	San Jose, CA, USA
Conf. info. (Date):	2005.03.03-2005.03.04

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