Applications of CPL mask technology for sub-65nm gate imaging

Applications of CPL mask technology for sub-65nm gate imaging

Author(s):

Litt, L. C. ( Freescale Semiconductor (USA) )

Conley, W. ( Freescale Semiconductor (USA) )

Wu, W. ( Freescale Semiconductor (USA) )

Peters, R. ( Freescale Semiconductor (USA) )

Parker, C. ( Freescale Semiconductor (USA) )

Cobb, J. ( Freescale Semiconductor (USA) )

Kasprowicz, B. S. ( Photronics (USA) )

van den Broeke, D. ( ASML USA) and ASML MaskTools, Inc. (USA) )

Park, J. C. ( ASML USA) and ASML MaskTools, Inc. (USA) )

Karur-Shanmugam, R. ( Univ. of Texas af Dallas (USA) )

5 more

Publication title:

Optical microlithography XVIII : 1-4 March, 2005, San Jose, California, USA

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

5754

Pub. Year:

2005

Pt.:

3

Page(from):

1459

Page(to):

1468

Pages:

10

Pub. info.:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819457349 [0819457345]

Language:

English

Call no.:

P63600/5754

Type:

Conference Proceedings

Details

TDL ID:	ZA00014979
Series ID:	PA00000029
Conf. info. (Name):	SPIE Advanced Lithography : Advances in resist technology and processing
Conf. info. (Number):	2005 : 18th
Conf. info. (Venue):	San Jose, CA, USA
Conf. info. (Date):	2005.03.01-2005.03.04
Note for article:	18th Optical microlithography,1-4 March, 2005, San Jose, California, USA

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